FIGS. 7(a)-7(i) are sectional views illustrating process steps in a prior art method of fabricating a field effect transistor (hereinafter referred to as an FET).
Initially, as illustrated in FIG. 7(a), an n type GaAs layer 2 having a dopant concentration of 3.times.10.sup.17 cm.sup.-3 and a thickness of 3000 .ANG. is grown on a semi-insulating GaAs substrate 1 by molecular beam epitaxy (hereinafter referred to as MBE). Thereafter, as illustrated in FIG. 7(b), an SiO.sub.2 film 3 having a thickness of about 3000 .ANG. is deposited over the n type GaAs layer 2 by plasma chemical vapor deposition (hereinafter referred to as plasma CVD).
In the step of FIG. 7(c), a resist pattern 4 with an opening 4a having a prescribed width is formed on the n type GaAs layer 2 by conventional photolithographic techniques.
Using the resist pattern 4 as a mask, the SiO.sub.2 film 3 is subjected to reactive ion etching with a gas mixture of CHF.sub.3 and O.sub.2 through the opening 4a, forming an opening 3a in the SiO.sub.2 film 3, followed by removal of the resist pattern 4 (FIG. 7(d)).
In the step of FIG. 7(e), using the SiO.sub.2 film 3 as a mask, the n type GaAs layer 2 exposed in the opening 3a is subjected to dry etching to remove a prescribed portion of the GaAs layer 2, thereby forming a recess 2a. Thereafter, an SiO.sub.2 film 5 about 5000 .ANG. thick is deposited on the SiO.sub.2 film 3 and in the recess 2a.
In the step of FIG. 7(f), the SiO.sub.2 film 5 is subjected to reactive ion etching with a gas mixture of CHF.sub.3 and O.sub.2. Since the etching proceeds anisotropically in a direction perpendicular to the surface of the n type GaAs layer 2, portions 5a of the SiO.sub.2 film 5 are left on the opposite side surfaces of the recess 2a. These portions 5a are called side walls hereinafter.
Thereafter, a WSi film 6 and an Au film 7 are successively sputtered on the SiO.sub.2 film 3, on the side walls 5a, and on the bottom of the recess 2a (FIG. 7(g)), and the Au film 7 and the WSi film 6 are patterned by ion milling and reactive ion etching, respectively, resulting in a gate electrode 8 as shown in FIG. 7(h).
After removal of the SiO.sub.2 film 3 and the side walls 5a with an aqueous buffered HF (BHF) solution, source and drain electrodes 9a and 9b comprising an ohmic metal are formed on the GaAs layer 2 at the opposite sides of the gate electrode 8 to complete an FET 100 shown in FIG. 7(i).
In the prior art method of fabricating an FET, the side walls 5a are formed on the opposite side surfaces of the recess 2a, and the gate electrode 8 is formed on a part of the bottom of the recess between the side walls 5a. In this process, a gate electrode having an accurately reduced gate length is formed in the recess 2a with high reliability. More specifically, since the width of the side wall 5a depends on the thickness of the SiO.sub.2 film 5, the width of the side wall 5a can be varied by verifying the thickness of the SiO.sub.2 film 5. Therefore, an opening region having a width equal to a desired gate length of the gate electrode 8 is formed at the bottom of the recess 2 with high accuracy.
However, in order to reduce the gate length with high accuracy, both accurate control of the thickness of the SiO.sub.2 film 5 in the step of FIG. 7(e) and strong anisotropy of the reaction ion etching of the SiO.sub.2 film in the step of FIG. 7(f) are required. In this reactive ion etching, if the applied RF voltage is increased and the pressure of the etching gas is reduced to increase the anisotropy of the etching, the etching selectivity between the n type GaAs layer 2 and the SiO.sub.2 film 5 is reduced, so that not only the SiO.sub.2 film 5 but also the n type GaAs layer 2 are etched as shown by a dotted circle A in FIG. 7(f). In this case, the thickness of the n type GaAs active layer 2 beneath the gate electrode is varied in a completed transistor, resulting in variations in the operating characteristics. To be specific, in the above-described n type GaAs active layer 2 having a dopant concentration of 3.times.10.sup.17 cm.sup.-3, when the active layer 2 is excessively etched by 13 .ANG. in the direction perpendicular to the surface of the active layer 2, the current of the transistor varies by about 1 mA per gate width of unit 100 .mu.m. This variation can be reduced to some extent by reducing the dopant concentration of the active layer. That is, when the dopant concentration of the active layer is reduced, current flowing per unit thickness is reduced, whereby the variation in the current to the variation in the thickness of the active layer is reduced. However, when the dopant concentration of the active layer is reduced, the transconductance of the transistor is degraded, and the gain during RF operation of the transistor is reduced.
Generally, in an FET, the gate breakdown voltage that has a considerable influence on the output characteristics increases with an increase in the distance between an edge of a gate electrode and an edge of a gate recess (hereinafter referred to as a gate edge to recess edge distance). Therefore, also in the prior art method shown in FIGS. 7(a)-7(i), the gate edge to recess edge distance can be increased by increasing the width of the recess 2a. However, in order to increase the gate edge to recess edge distance in the prior art method, both the width of the recess 2a and the width of the side wall 5a must be increased. Since the width of the side wall 5a depends on the thickness of the SiO.sub.2 film 5, the thickness of the SiO.sub.2 film 5 must be increased to increase the width of the side wall 5a. Then, the etching precision in the etching of the SiO.sub.2 film 5 (FIG. 7(f)) is lowered, resulting in a variation in the gate length and an increase in the etching time.
It is well known that the gate breakdown voltage increases with a reduction in the dopant impurity concentration at the interface between the active layer and the gate electrode. In a prior art method, however, the increase in the gate breakdown voltage is achieved by inserting a low dopant concentration layer in an active layer and forming a gate electrode contacting the low dopant concentration layer. In this case, the low dopant concentration layer is present in the active layer at portions beneath source and drain electrodes, so that the gate-to-source resistance increases.